Reed-Solomon (RS) codes are a powerful class of multiple error-correcting codes. RS codes have a wide range of applications, such as optical communications, and wireless communications magnetic recording systems. When applying systematic Reed-Solomon encoding, data is transmitted in codewords that represent a combination of the original data symbols and a number of parity symbols. An RS code that uses 2t parity symbols is commonly correctable to t errors. The value of t is commonly called a maximum error limit. An RS decoder uses the 2t parity symbols to correct a received message, even if the received message experiences up to t errors during transmission.
In many modern communication systems, RS decoders use extra information along with received data. A reliability value is calculated for each received data symbol. RS decoders that use the reliability information are called soft decoders. Received data symbols with very small reliability are called erasures. If a particular data symbol in a received codeword is known to be an erasure, a value of the particular symbol is ignored when the RS decoder attempts to decode the codeword. If ν errors and ρ erasures occur during transmission of a codeword, the codeword can be corrected if and only if ν+ρ≦2t. RS decoders that use information about erasures are called error-and-erasure decoders.
Referring to FIG. 1, a block diagram of a conventional RS decoder 20 is shown. The decoder 20 includes a circuit 22 for Syndrome Calculations (SC), a circuit 24 for Key Equation Solving (KES), a circuit 26 for Error Correction (EC) and a First-In-First-Out (FIFO) buffer 28. In operation, the circuit 22 accepts a received codeword symbol-by-symbol and provides a set of syndromes to the circuit 24. The circuit 24 calculates an error locator polynomial based on the syndromes. The error locator polynomial provides the positions of errors. The circuit 24 implements a key equation solving technique, such as the Berlekamp-Massey technique, the Euclidian technique or the Peterson technique. The circuit 24 calculates an errata polynomial. The errata polynomial provides the magnitudes of errors in the error positions. The circuit 24 passes the errata polynomial to the circuit 26. The circuit 26 uses the errata polynomial to perform data corrections. A binary failure signal (i.e., FAIL) of the circuit 26 is asserted if a number of corrected data symbols is more than the maximum error limit.
Referring to FIG. 2, a block diagram of a conventional soft RS decoder 30 is shown. The decoder 30 includes the circuit 22, the circuit 24, the circuit 26 and the FIFO 28. An additional FIFO 32 saves the codewords from the FIFO 28. FIFOs 34 and 36 save reliability information received in a signal (i.e., RELIABILITY). A Soft Decoder (SD) circuit 38 decodes each error-filled codeword that the circuit 26 fails to correct. While the circuit 38 works on an error-filled codeword, the circuits 22 to 28 can process other codewords. The circuit 38 conventionally has a software implementation due to cost. As a result, software decisions are relatively slow. The slow decisions are typically acceptable under an assumption that the circuit 26 rarely fails to correct all of the errors in the codewords.